Do you understand timing constraints. Asked a few questions about them.
Asic Engineer Interview Questions
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Basic FIFO and CDC questions
Question asked: SV -> function can take fork_join?y/n ->to find the bit to represent 4069 = 2^(x) or log 2 base (32) ->Malloc() ->write a integer queue : rand int q[$]; -> task and functions UVM: Sequencer- Driver connection phasing name 3 base class related question
Explain POCV coefficient based calculation for an actual timing report.
Gave a standard fifo design and told me to explain how i'll write testbench for that
design uvm driver
coding
about muxes, decoder logic of RAMs as well as testing it
Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
Design a Counter verification environment.
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