Design a FIFO hardware
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False paths and Multiple cycle path examples.
Design a state machine to detect bit sequence. How do you verify it?
How to make nor gate using two input mux
Personal research, DVFS, CDC, metastable, asynchronous FIFO, synchronizer, level shifter, clock gating, power gating, dynamic power, leakage power.
all about resume, STA, DFT, Pipelining
Going over the resume in detail
Synchronous ans Asycnchronous FIFO design and verification.
There were no out of the box questions.
calculate set up , hold in terms of some 10 parameters.
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