(Unexpected) What the types of caches?
Asic Design Verification Engineer Interview Questions
97 asic design verification engineer interview questions shared by candidates
What did you do at your previous co-op employer?
Check the awareness of applying pre and post randomization in variables in uvm_object.
How to verify a design? What do you know about your verification env? Do I know any AMBA protocol? Do I use shell script? or any other script language?
How do you convince design team that a DUT has been thoroughly verified?
All the interviewers are Indians and were really nice. I had a really good conversation each interview is about an hour. Everyone had a set of questions prepared and asking me to solve. 1. Full SV - fork join_none, virutal functions, $cast, static variable, Cache size - direct mapping, MESI FSM, constarints, parity check - post randomize 2. STA - hold violations, max freq, FIFO depth, metasibility 3. DUT - muti master muti slave bridge verification - draw the env and testcases, AXI signals 4. UVM - phases, AXI why not APB?, AXI lite vs. AXI 3.0, Driver code, coverage class and do cross coverage. 5. HR -> about team work, resources you used in a project, set back you faced. Explained most employee benefits, applying for H1B and green card, etc
How to do numerous tasks and kill off 1 task if any finish. Then wait for all to finish.
Write UVM Monitor for the defined case.
About digital,verilog,system verilog questions In sv oops concepts
they focused a lot on OOP, which is unexpected given the title that I applied.
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