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Asic Physical Design Engineer Interview Questions

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34 asic physical design engineer interview questions shared by candidates

Tell me about yourself and work experience? Explain ASIC flow? What is Scan chain insertion? USe? What is scan chain reordering? Why macros are placed preferably at boundary and not at centre? What all physical only cells you cam across ? Explain? Checks before placement? How do you fix timing at Place? Difference between CCD and CTS? What is HFNS? Why it is not done at syn? Aim of CTS? What happens in route? What are NDR ? Explain side flows? Types of placement blockages? What is derate? what is LVS? what is FEV? Kind of buffers used for CTS? How do you select them?
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ASIC Physical Design Engineer II

Interviewed at SignOff Semiconductors

4★
Jul 14, 2020

Tell me about yourself and work experience? Explain ASIC flow? What is Scan chain insertion? USe? What is scan chain reordering? Why macros are placed preferably at boundary and not at centre? What all physical only cells you cam across ? Explain? Checks before placement? How do you fix timing at Place? Difference between CCD and CTS? What is HFNS? Why it is not done at syn? Aim of CTS? What happens in route? What are NDR ? Explain side flows? Types of placement blockages? What is derate? what is LVS? what is FEV? Kind of buffers used for CTS? How do you select them?

1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.
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ASIC Physical Design Engineer (Hardware Engineer)

Interviewed at NVIDIA

4.4★
Nov 8, 2013

1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.

1. what is the max freq of a given circuit.(setup and hold analysis related) 2. one question was related to stuck at fault. we need to find out the input test pattern in order to detect the stuck at fault of given circuit. 3. IN1?A:IN2?B:IN3?C:1'b0 How many 2:1 mux are required to implement this? 4 one question was related to FIFO Depth calculation. 5. In a given circuit to meet timing how many no of re timing flops need to be inserted?(you should be clear with setup analysis) 6. Questions were related to transistor sizing and cache memory hit and miss ratio. 7. One puzzle was also asked of Annual function and van related(don't remember exactly. :p)
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Staff ASIC Physical Design Engineer (ASIC PD Engineer)

Interviewed at NVIDIA

4.4★
Jan 16, 2021

1. what is the max freq of a given circuit.(setup and hold analysis related) 2. one question was related to stuck at fault. we need to find out the input test pattern in order to detect the stuck at fault of given circuit. 3. IN1?A:IN2?B:IN3?C:1'b0 How many 2:1 mux are required to implement this? 4 one question was related to FIFO Depth calculation. 5. In a given circuit to meet timing how many no of re timing flops need to be inserted?(you should be clear with setup analysis) 6. Questions were related to transistor sizing and cache memory hit and miss ratio. 7. One puzzle was also asked of Annual function and van related(don't remember exactly. :p)

Process and Improvements - Examples of how you've improved processes - Thoughts on how current core processes could be enhanced - Creative and critical thinking abilities Physical Design, Power and Timing - Power optimization strategies - Timing challenges in high-frequency designs - Understanding RTL vs. PD in cores and SoC PD Flow and Fundamentals - Synthesis Design Compiler - Backend flow: DRC, LVS - Verilog (read and edit) - Primetime, STA (Static Timing Analysis) - High-speed designs (3GHz+) Structured Problem Solving - Real-world examples of problem-solving from past experience - On-the-spot problem-solving scenarios - Demonstrating adaptability and logical thinking Also topics about CTS including ICG cloning
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Staff ASIC Physical Design Engineer

Interviewed at AMD

4★
May 21, 2025

Process and Improvements - Examples of how you've improved processes - Thoughts on how current core processes could be enhanced - Creative and critical thinking abilities Physical Design, Power and Timing - Power optimization strategies - Timing challenges in high-frequency designs - Understanding RTL vs. PD in cores and SoC PD Flow and Fundamentals - Synthesis Design Compiler - Backend flow: DRC, LVS - Verilog (read and edit) - Primetime, STA (Static Timing Analysis) - High-speed designs (3GHz+) Structured Problem Solving - Real-world examples of problem-solving from past experience - On-the-spot problem-solving scenarios - Demonstrating adaptability and logical thinking Also topics about CTS including ICG cloning

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