CMOS Inverter , how to reduce the drive strength of Minimum size inverter
Physical Design Engineer Interview Questions
594 physical design engineer interview questions shared by candidates
Explain a scenario where hold violation can be fixed by lowering frequency.
Draw a two-put NAND gate and size it, assuming the ratio of PMOS/NMOS is 2 in inverter. Then suppose two input are A and B for NMOS and PMOS. A is close to output and B is close to ground, input A change from 0 to 1 at t=t1, input B change from 0 to 1 at t =t1 (t1 > t0). Describe how the output change. Then input B changes from 0 to 1 first then input A changes from 0 to 1. Describe how the output changes. Are there any differences between these two scenarios?
build the func f=(ab+c`)` using min mux 2:1
What's power gating and clock gating. Briefly explain setup time and hold time violation. Briefly describe what is physical design. Sequence Detector. And some questions about my project.
talk about the clock distribution
Draw an inverter. Then switch the position of NMOS and PMOS. Describe the circuit.
You are provided with one XOR gate, one OR gate and one NOR gate. Please build a NAND gate.
how do you Implement blocks using IC Design Compiler?
Your work experience in latest technology, design process, tools used, issues seen and how they were resolved
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