Array, system verilog,uvm, mailbox Queue fifo configdb etc
Asic Verification Engineer Interview Questions
229 asic verification engineer interview questions shared by candidates
Question on C programming * what is the difference between call by value and call by reference? Questions related to electronics? * combinational circuits * Sequential circuits *Implement 16:1 MUX using 4:1 mux *Explain S-R fliflop . * Differentiate between == and ===
What is the one thing that you are proud of yourself during the learning process ?
A block diagram of a protocol block was given and was asked to write a SystemVerilog transactor code.
Domande legate a quali strategie usare per testare funzionalità di ASIC
Questions related to Pipelining, Interrupt Handling.
Write constraints for unique elements in an array. Write assertions for different scenarios of AXI protocol. Basics of UVM including testbench components, phases, TLM ports.
Questions on protocols like API, AXI, AHB, API, UART.
1)Driver sequencer handshake.
* job experience and roles * how do u verify a scheduler * A block has inputs of network pkts and buffers/pipelines them through an RTL. RTL has counters which will tell how many packets are sent. How to verify? (Counters Read => count. Write => clear) How to verify counts? what cases will u test? * Given a sys verilog code for a memory model and asked to implement read/write/move functions and write checks
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