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Asic Verification Engineer Interview Questions
229 asic verification engineer interview questions shared by candidates
Question regarding Logic design, Verilog ,State Machine- pattern detection, Comp Arch- Pipeline, hazards, cache, associativity, Basic Perl were asked.
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
Constraint randomization based question linking to AXI and memory filling
Node insertion in linked list. Fibonacci series function, hardware to generate Fibonacci series, prime number generation hardware , STA concepts, clock domain crossing, use of synchronizes, skew and setup hold time violation.
Explain past work experience and Project details.
Scripting questions on 2D hashes and asked for coding in perl/python. Basic questions on STA
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
My previous experience, as well as a few mock examples related to verification and what my process would be
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