Basics of UVM and SV
Asic Verification Engineer Interview Questions
229 asic verification engineer interview questions shared by candidates
Tell us about yourself.
Basic system Verilog and uvm.
FSM problem. i had to write the state machime to find if the number was divisible by 3 or not. sequence detector for divisible by 3 numbers in cummulative manner.
what is a asic design?
technical- counter, data types (enum, struct), blocking and non blocking assignments. Aptitude- mixture and allegation, ratio and proportion, distance and speed, percentage, population based question.
How would you stress test a safe lock?
Tell me about yourself.
Regarding testbench in sv and uvm
I was asked to give a brief on PCIe protocol
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