Phone interviews : CMOS basics, usual some gate/logic using one gate, timing related questions, FIFO depth, max in array, palindrome Onsite : CDC - a lot on various techniques and improvements from one to another, clock MUX logic, Clock dividers, FSM , Timing related question based on designs above
- Questions on different types of cache - Difference b/w them - Explain inclusive and exclusive caches
Asked about Cache implementation (since I had a project on cache implementation using verilog)
In C, write code to find out if a string is palindrome or not
Asked basic questions based on resume. The position required CPU architecture knowledge. I hadn't taken any of those courses, so interviewer asked only IC designing questoins.
describe the equations for setup time and hold time on a registered path with clock skew
whats the ad and disad of using large cache and small cache
Clock skew? Good or bad for a circuit with 2 flops and combinational logic in between.
There are two questions, one is about FSM, you should design a FSM with 5 bit, its function is to counter the even number of 0 or 1, e.g. 2, 4, 6....
What will happen if a default case is not used in a case statement?
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