calculate the addressing of a 4-way set associative cache for a given size
Asic Engineer Interview Questions
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The second questions is about Combination logic, to conter the first 1 bit in the 8192 data stream. the output it in 13-bit index. it is a little difficult!
FPGA designers that use Verilog are typically not good at using object oriented languages like System Verilog.
Write a verilog code to swap data with and without a temp register.
fifi design
Design clock switchers without any glitch.
Calculate the number of logic 1's in a given input using combinational logic only. And some basic logic based questions
Design a hardware to detect how many bits are 1 with only combination logic design
Questions 1. Sequence detector for 1001 overlapping sequence (fsm design + verilog code) 2. Basic STA questions on setup and hold time like if in a silicon a path is failing, what would be the first step that you will do to check it is a setup failure.
There are 8 bits inputs ,only use full adder to detect how many logic 1's
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