Design a circuit that would count 1 every time another counter counts from 0 to 255. One of the counter is working at higher frequency than the other.
Asic Engineer Interview Questions
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(Unexpected) What the types of caches?
Suppose you discover that the circuit you are testing in the lab does not function correctly due to a hold time violation. What would be the first thing you try to make the circuit work?
Differentiate between = and => sings in verilog.
How do I connect two designs working at different clock speeds ?
Write the base-11 representation of the decimal number 175.
Suppose you have an infinite bit stream representing a binary number (LSB first), and that stream is entering your machine one bit per clock cycle, and you want your state machine to output a 1 any time the total is divisible by 5, otherwise output zero.
using a simple logic gate, convert a SET type flop to a RESET type flop
How to check if a fabricated chip has a hold time violation, and how to fix it.
1st is HR, ask about why Nvidia? expected salary, immigration status, graduation date, etc. 2nd ask about verification methodology (UVM, OVM), system verilog (passing obj as function argument, different type of fork-join, polymorphism etc), use and function of interface in testbench. 3rd ask about arbiter design, setup/hold time, basic logic design, 4rd ask about programming (how to find loops in a linked list), basic C programming and divide by 3 divider. 5th is hiring manager, talk about positions, teams and their products. ask about basic logic design, verilog(syn, asyn, blocking, non-blocking), transistor level design of registers and what could be problem with that design. 6th dude is a funny guy who ask about nothing but just keep talking about the team, what he has done and what he like and don't like about his job, etc. Most difficult: design divide by 3 divider with 50% duty cycle, I don't know how to do that, and the recruiter change the duty cycle to 66%, and I finished it.
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