CDC- slow to fast, fast to slow crossing. Sycn FIFO and ASycn FIFO - Differences
Soc Design Engineer Interview Questions
100 soc design engineer interview questions shared by candidates
UVM Concepts and Work Experience of previous project
basics of cmos inverter, digital circuits, verilog, RTL to GDSll flow.
LRU policy, programming, state machine encoding
Basic Verilog questions, FSM, Synchronizers, Clock Domain Crossing, Sequence detectors, Clock divider circuits, FIFO, Async FIFO, Circuit to detect the number of 1's using adders and then using only combinational logic, Transpose a Matrix using C. I was asked to code on almost all of the topics mentioned above.
Some system verilog Questions
Basically covered VLSI basics, ASIC flow basics (each step) and scripting. Friendly chat for behavioral interview.
Program to differentiate even and odd number Draw and explain NOT and NAND gate Draw a stick diagram for NOT gate Find ways to make NAND gate a NOT gate Explain methods of verifying your design, such as DFT Scan path.
Resume shortlist were there Digital design questions were there Sta questions were there Verilog questions were there Computer architecture questions were there Device physics questions were there Some puzzles were there Hr questions were there
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