All the interviewers are Indians and were really nice. I had a really good conversation each interview is about an hour. Everyone had a set of questions prepared and asking me to solve. 1. Full SV - fork join_none, virutal functions, $cast, static variable, Cache size - direct mapping, MESI FSM, constarints, parity check - post randomize 2. STA - hold violations, max freq, FIFO depth, metasibility 3. DUT - muti master muti slave bridge verification - draw the env and testcases, AXI signals 4. UVM - phases, AXI why not APB?, AXI lite vs. AXI 3.0, Driver code, coverage class and do cross coverage. 5. HR -> about team work, resources you used in a project, set back you faced. Explained most employee benefits, applying for H1B and green card, etc
Asic Verification Engineer Interview Questions
229 asic verification engineer interview questions shared by candidates
How to do numerous tasks and kill off 1 task if any finish. Then wait for all to finish.
Write UVM Monitor for the defined case.
Technical
Salary negotiation. Do not hesitate to ask more than industry standard, no matter what is your current CTC
Write a Verilog code to detect a sequence (for FSM) Verilog code for flip-flops Questions related to digital electronics
digital, sv, verilog, UVM questions.
About digital,verilog,system verilog questions In sv oops concepts
Design a FSM of Moore Machine to detect 0110 sequence.
Types of coverage?
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