Coding in C to output Fibonacci
Asic Verification Engineer Interview Questions
229 asic verification engineer interview questions shared by candidates
Logic question to verify the design How would you verify 3 blocks with incorrect label ? suppose one with apple 2 with orange 3 with apple & orange.
tell me about uvm testbench top
What Is UVM? What Is the Advantage Of UVM?
Knowledge on OOPs concept. encapsulation and polymorphism. Function overload or overriding - Virtual, and non virtual function . Given a transmission of send and recv of a signal from 1 to 15 timeslots, find latency of signal from send to recv and determine and min and max latency . Probably looking for knowledge in counter and loops and logical thinking in the short span
What is the difference between Flip Flop and Latch? What is the difference between Synchronous and Asynchronous circuits?
Hr Round: What are your plans for your masters? Do you know what our company does? Any problem in relocating? What are your strengths and weaknesses?
Basic questions on Digital Electronics: making gates out of NAND and NOR gates, Setup and Hold time analysis.
Basic questions related to System Verilog and UVM
Design a Neural Network for a system.
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