2 input NAND gate, which states will have how much leakage power.
Asic Physical Design Engineer Interview Questions
34 asic physical design engineer interview questions shared by candidates
What's the purpose of Placement and what do we care about Placement.
what are the impacts of using very tight skew constraints
pd flow and physical verification questions
Tell me abuot your self
Questions regarding library creating and area of the cells in the library
Antenna Effect, latch up
Explain POCV coefficient based calculation for an actual timing report.
Why you do clk gating in your design
How to determine which register you want to gate in netlist ?
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