design async-fifo and sync-fifo in circuit level
Asic Engineer Interview Questions
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Systen verilog - uvm questions
How can you use an inverter in linear region?
Detect the leading one in a sequence. Find the second smallest number in an array. Determine whether a infinite sequence is the multiple of 5.
How do design async logic?
Do you know verilog?
1 question/quiz math related, 1 verilog code what it does and questions, 1 block diagram design and improvements, extensive talking through the behavioural part of the aptitude test with the hr manager, some sort of profiling.
design a statemachine to detect the pattern "101" in a 1-bit input stream.
about all the flow from beginning to end
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