Focus was on physical design.
Asic Engineer Interview Questions
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Questions on PCIe, CDC, Pipeline
State Machine. How to verify a piece of logic.
Design palindrome pattern recognition circuits and verify that circuit.
There weren't any very difficult or unexpected questions.
Name the data hazards
Timing closure. How noise(cross-talk) affect setup/hold? How metal dimension affect timing?
Write verilog code for implementing a NAND gate using a MUX
Write a uvm driver for a simple valid-ready protocol. - When data is available assert the valid - Keep the data stable and valid high until ready is asserted - De-assert the valid once ready is asserted interface if input clk; logic [15:0] Data; logic Valid; logic Ready; endinterface
Explain metastability and crossing between clock domains
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