FIFO questions
Asic Engineer Interview Questions
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What is a NAND gate
they focused a lot on OOP, which is unexpected given the title that I applied.
How to bring a signal from one clock domain to another
Write some codes to explain how to design asynchronous FIFO.
-Make a AND/OR gate out of muxes -Count the number of 1's in a 7 bit number using only full adders
how to design the next generation product with 2 times of throughput?
Who does CPPR affect on a noise glitch
Launch 5 (t1,t2,t3,t4,t5) tasks in parallel, wait for 4 of the tasks to be done and kill the task t3.
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