Standard digital design questions: 1. FSM 2. Multiplier design/questions 3. sync vs async reset
Asic Engineer Interview Questions
1,075 asic engineer interview questions shared by candidates
Cache coherency, mapping techniques, metastability, cdc, synchronizers,
1. explain synthesis flow in ASIC 2. Explain STA and what tools do you use 3. significance of physically aware netlist over regular netlist 4. explain setup and hold time 5. how will you solve critical path problems using PT
Design sequence detector with logic circuit diagram
Designing a master-slave circuit for a particular output waveform.
How to debug a timing violation in the lab?
They asked me questions related to Static Timing Analysis. For example, things like calculating setup time and hold time slack for a path in a digital circuit.
Digital design basics, UVM structure, OOPs
Basic Verilog code questions, such as latch inferences, correct assignations (not mixing blocking/non blocking), FSM, etc
CDC and related concepts. Clock main issues, metastability, glitching, etc, and the possible solutions
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