Flow of current in a layout ( given randomly by the interviewer)
Physical Design Engineer Interview Questions
595 physical design engineer interview questions shared by candidates
What is setup and hold time? How to fix any timing violation? Explain the sanity checks for each stage of the PD flow? What is crosstalk, EM, antenna violation?
layout related questions, and generic cmos question
Tell any 5 commands and how to validate floorplan
PNR flow, Sta, OCV, AOCV Internship experience based questions Physical verification and Routing
Self intro Input file Floorplan Guidelines to macro Physical cells Taps cells Latchup effect Placement Output reports of placement What is setup and hold How to overcome setup violations
Question related to previous project regarding how many issue you faced
All the concepts of STA
What is pd flow and explain them with their input and outputs
If the combination logic between 2 FF's is cut like an interface, how do you set_input_delay and set_output_delay for left and right partitions. The clock is the same for both.
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