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Physical Design Engineer Interview Questions
595 physical design engineer interview questions shared by candidates
AOCV and POCV in detail
What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.
they ask the inputs into the tools for different steps of physical design.
Setup time vs hold time/how to fix?
What are the differences between buffers and inverters? A ~30 minute discussion on this question followed.
What are some examples of scripts you have wrote, and give some scripting solutions to a problem, e.g. parsing timing reports.
What if the gap between the macros increases in the floor placement..?
Questions on Level Shifters, clock domain crossing scenarios with logic circuits .
How is uncertainty determined.
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