STA, PNR, and the Antenna effect. Basic logical gate circuit.
Physical Design Engineer Interview Questions
595 physical design engineer interview questions shared by candidates
Flow of current in a layout ( given randomly by the interviewer)
Phone screening 1. Questions about previous work experiences, digital circuit/layout design. 1:1 Technical interviews 1. RC circuits. Response to step input signal. 2. Transistor sizing for better setup/hold times. 3. Layout design of NAND3/NOR3 gates in different styles 4. Elmore delay of complex gates. 5. Standard cell library architecture choices and tradeoffs 6. Physical verification of standard cell libraries 7. DFM/DFD questions 8. Perl/Tcl and EDA tool related questions
they ask the inputs into the tools for different steps of physical design.
Setup time vs hold time/how to fix?
basic cmos circuits and power consumptions
How to combine nmos and pmos with only one substrate?
Describe the transistor IV cruve
Make a CMOS inverter with MOSFETs
Self intro Input file Floorplan Guidelines to macro Physical cells Taps cells Latchup effect Placement Output reports of placement What is setup and hold How to overcome setup violations
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