2nd phone interview: 1 unit with 9ns delay vs 3 units with delays 2ns, 4ns, 3ns. Which has better throughput and how much?
Design Verification Engineer Interview Questions
950 design verification engineer interview questions shared by candidates
Write UVM Monitor for the defined case.
If you have a series of commands working on data (an image), how do you prevent commands working on the same data at the same time?
What is the difference between strong and weak memory models?
show how to implement a module that yields the dot product of two vectors
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Some digital questions and verilog
They mostly concentrate on your resume , computer architecture and digital design basics
uvm architecture nd sv nd digital verilog
Focus mainly on Digital Electronics,basic Programming concepts if u have mentioned in your resume.Sometimes,concepts of Verilog and VHDL programming are also asked.
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