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Design Verification Engineer Interview Questions
949 design verification engineer interview questions shared by candidates
Asked me questions on Tessent tool
My experience was bad in 2 rounds otherwise good in other 3 rounds.
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
Not Applicable and confidential as per norms
About digital electronics for VLSI domain
Why modport is used? What is polymorphism? What is deep copying ? what is inheritence? Why we are writing interface? Different Phases in UVM? Which phase are task and which are functions?
How to convert hexadecimal to decimal.
- about SV, FIFO design, arbiter design
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