Explain gray code and FIFO techinique?
Design Verification Engineer Interview Questions
950 design verification engineer interview questions shared by candidates
How to do numerous tasks and kill off 1 task if any finish. Then wait for all to finish.
implement 4*1 mux using ternary operator
Write a code in any programming language to square every second number in a list and then add all the numbers in that list. 1h given for this task. The subsequent question asks about your solution, what was the approach, method, and what would you do differently.
( I have just passed out from BTech) First round: 1) Asked about college. 2) Implement 7:1 Mux using 2:1 mux 3) Why verilog is used in this field? 4) Difference between latch and flip flop ( with waveforms). 5) You had C in engineering, why didn't you include it in your resume? C has more use , right? 6) About Major Project ( Why it is not related to VLSI?) 7) Frequency Division Circuit 8) What is the default value of wire? 9) What is the default value of reg? 10 ) Convert one hexadecimal number to binary Second Round 1) Tell me about yourself. ( I was enrolled in a program, asked about that program in detail.) 2) Design an asynchronous flipflop in verilog. 3) What is setup time, hold time? 4) What are the different types of delay and explain them? 5) Differences between RISC and CISC. 6) What are the application of counters? 7) What is a shift register explain its operation with a suitable circuit diagram? 8) Psuedo code for finding prime numbers from 1 to 100. 9) What is LSFR? 10) What is pipelining how it is implemented? 11) Could you draw the symbol of CMOS inverter? 12) What is CMOS? 13) Do you really know python? 14) What did you do in MATLAB? 15) Certifications are not enough, did you do any project related to this? Third Round: 1) Gave an AND OR circuit and asked to convert it into a MUX. 2) Difference between latch and flipflop 3) Draw a latch using only NAND gates. 4) Draw a D latch. 5) Psuedocode for checking a string in a the contents of a file in a directory of files. 6) Is MATLAB a tool or language?
2nd phone interview: 1 unit with 9ns delay vs 3 units with delays 2ns, 4ns, 3ns. Which has better throughput and how much?
How would you verify a multistage cache with multiple masters?
What is verification about? What are the components of design verification? What is coverage?
show how to implement a module that yields the dot product of two vectors
If you have a series of commands working on data (an image), how do you prevent commands working on the same data at the same time?
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