Q. Describe your test plan for a FIFO
Design Verification Engineer Interview Questions
950 design verification engineer interview questions shared by candidates
setup/hold time ;verification coverages and types
write HDL code for a FSM
FSM, SystermVerilog, and software leetcode related questions.
How the UVM sequencer and the sequence handshake happens
What's your name , is it [name] ?
implementation of driver class based on the figure they gave
UVM based questions and Assertions and constraints
Design an FSM for a 2-clock system
There are block box modules, and you know nothing about what they are doing, behaior, output, input. Can you create a verification TB for it?
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