Computer Architecture. OOPs. System Verilog and UVM. Graphics Architecture .
Design Verification Engineer Interview Questions
950 design verification engineer interview questions shared by candidates
Q1. FIFO depth, given read and write rates for a burst of x writes Q2. a=0; b=0; c=1; #1 a=c; #1 b =a; (Give waveforms) Q3. a<=0; b<=0; c<=1; #1 a<=c; #1 b< =a; (Give waveforms) Q4. a=0; b=0; c=1; a= #1 c; b=#1 a; (Give waveforms) Q5. a<=0; b<=0; c<=1; a<= #1 c; b<=#1 a; (Give waveforms) Q6. You have incoming bit stream. You can't store them. You get a new bit at every clock edge, find modulo 5 of the updated number everytime. Eg, if bitstream is 10111, you find modulo of 1, then 10, then 101 and so on..
Describes one of your projects
Write TB for one of the projects from past experience . Describe its features and implement DUT interface connections and build TB on whiteboard .
DV related, protocols, sv, uvm, axi,abp
Cache Coherency, UVM and TLM related, SV concepts, Past projects.
They asked about uvm fundamentals. They were looking for strong uvm experience and asked me to write code for scoreboard, monitor and asked about how to connect them.
design an electrical circuit with switches, voltage source for a particular application- wasn't expecting one since my area of expertise is mostly digital
2 signals, both only toggle once. At the first rising edge, start testbench; At the second falling edge, stop testbench. How?
Memory Consistency
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