What is the difference between SV function and Verilog function?
Design Verification Engineer Interview Questions
950 design verification engineer interview questions shared by candidates
TECH: 1. write a code that generates a random phone number 2. You have 4 processes: A, B, C, D. If any of them finishes kill B. When all of them are finished print Done. (use fork join) 3. inheritance, asks you when a child had the same function as a parent what will it print when it is called. what is different when the function is virtual. can a child object be assignment to a parent and vice versa? after the assignment you call the function and they ask you what will be printed 4. make a sequence for burst write and read, for a 32 bit (I cant remember but there was a number here also?) K memory. (you need to write an item first and then show how it is used in the sequence)
Verify a protocol and tell checkers
What did you do in the current position ?
Basic Computer Architecture questions. How to extend a 5 stage pipeline to 6 stages. Effects of doing that etc. A few programming questions.
DV related, protocols, sv, uvm, axi,abp
Write TB for one of the projects from past experience . Describe its features and implement DUT interface connections and build TB on whiteboard .
build a function that get: s - sum of puckets n - number of puckets MIN - minimu value of a pucket MAX - maximum value of a pucket return an array in length n that each pucket have a value between MIN and MAX and the sum of all puckets is s. all puckets are random.
They asked about uvm fundamentals. They were looking for strong uvm experience and asked me to write code for scoreboard, monitor and asked about how to connect them.
There are block box modules, and you know nothing about what they are doing, behaior, output, input. Can you create a verification TB for it?
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