Implement a state machine that detects modulo 5
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Why should i hire you?
Basic stuff about Verification and assertions
Basic system verilog and UVM based questions
How would you do your job in X project?
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
What is the difference between Mealy and Moore machines?
Uvm phasing process, different phases in uvm
What will you do if you made a big mistake?
write code which returns error if we got 10 packets within 10 seconds
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