Questions on constraints and assertions
Asic Verification Engineer Interview Questions
229 asic verification engineer interview questions shared by candidates
Designing multiple Gates or some basic logic using Multiplexers. Draw state Diagram & verilog code for 1010 sequence detector.
Explain about the AXI write process with signal descriptions
Question asked: SV -> function can take fork_join?y/n ->to find the bit to represent 4069 = 2^(x) or log 2 base (32) ->Malloc() ->write a integer queue : rand int q[$]; -> task and functions UVM: Sequencer- Driver connection phasing name 3 base class related question
Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
Design a Counter verification environment.
How to verify a fifo?
There were no out of the box questions.
What will affect power consumption?
Your'e given a matrix MxN of 0's and 1's. everytime you encounter 1 cell, you need to put 0's in the rows and columns.
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