Regarding testbench in sv and uvm
Asic Design Verification Engineer Interview Questions
97 asic design verification engineer interview questions shared by candidates
I was asked to give a brief on PCIe protocol
Array, system verilog,uvm, mailbox Queue fifo configdb etc
What is the one thing that you are proud of yourself during the learning process ?
Domande legate a quali strategie usare per testare funzionalità di ASIC
Questions related to Pipelining, Interrupt Handling.
Write constraints for unique elements in an array. Write assertions for different scenarios of AXI protocol. Basics of UVM including testbench components, phases, TLM ports.
Questions on protocols like API, AXI, AHB, API, UART.
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
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