Write a verilog code for dual Port ram using 2 single port ram
Asic Design Verification Engineer Interview Questions
97 asic design verification engineer interview questions shared by candidates
What is handshake mechanism in uvm and explain how to override
The interviewer asked some verification questions - those were nice; but then he also asked a software (i.e "cracking the coding interview") type of question. I'm not a Software Engineer
AI questions included about auto encoders, lstms, basics of neural network, convolutional neural networks etc.
Write a uvm driver for a simple valid-ready protocol. - When data is available assert the valid - Keep the data stable and valid high until ready is asserted - De-assert the valid once ready is asserted interface if input clk; logic [15:0] Data; logic Valid; logic Ready; endinterface
Some computer architecture questions like pipeline design and pipeline hazards
Python question and verilog question to implement the same thing
introduce your last position/ project?
It consisted of 2 rounds. In Round 1 they asked about basics of digital electronics, cro, osciloscope. In Round 2, they asked to code traffic light controller o verilog and discuss its area, power
Full adder code, Gave some verilog codes to debug and find errors, Digital questions and Aptitude is important
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