Launch 5 (t1,t2,t3,t4,t5) tasks in parallel, wait for 4 of the tasks to be done and kill the task t3.
Asic Design Verification Engineer Interview Questions
97 asic design verification engineer interview questions shared by candidates
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tell me about uvm testbench top
Knowledge on OOPs concept. encapsulation and polymorphism. Function overload or overriding - Virtual, and non virtual function . Given a transmission of send and recv of a signal from 1 to 15 timeslots, find latency of signal from send to recv and determine and min and max latency . Probably looking for knowledge in counter and loops and logical thinking in the short span
Basic questions related to System Verilog and UVM
Design a Neural Network for a system.
1. Memory design and block diagram 2.Verilog programming 3.C++ (oops concepts) 4.SV & UVM components
Difference between 8085MP and 8086
SV UVM APB AXI AHB
Related to SV + UVM + Puzzles + Perl and other scripting language
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