Basic questions related to System Verilog and UVM
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
Design a Neural Network for a system.
1. Memory design and block diagram 2.Verilog programming 3.C++ (oops concepts) 4.SV & UVM components
Difference between 8085MP and 8086
Unexpected: Depth of a couple of technical questions in terms of layers of complexities. With every solution, a wrinkle is added. Real problems are complex, and some times not in the field of candidates background.
What motivates you to join infinera?
Just prepare well on what all area you have worked. if you are not confident about one area just say you haven't worked
Describe your internship project
What is the relationship between read and write clock for different data widths in a FIFO?
SV UVM APB AXI AHB
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