How do you implement the analog components of a PLL which are non-synthesizable in verilog?
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
Q: ASIC flow? Q: Hands - on code ; RTL
What is cmos. Realization of gates using cmos and gates using mux. Demultiplexer?
7. Majorly on projects done
1. FSM design and comparision of FSM state encoding techniques
What do your parents do for a living?
the flow of asic design in details .
BJT working methodology, ohms law exact defination
What is crosstalk delay and how to fix?
design a state machine and write Verilog code.
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