How to make an AND gate with only XOR gates
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
varies and based on JD
I felt the most difficult question was about different metal layers and their properties
Write some verilog for a 3 to 1 arbiter, with a priority client and 2 clients in a round robin.
Knowledge on OOPs concept. encapsulation and polymorphism. Function overload or overriding - Virtual, and non virtual function . Given a transmission of send and recv of a signal from 1 to 15 timeslots, find latency of signal from send to recv and determine and min and max latency . Probably looking for knowledge in counter and loops and logical thinking in the short span
Explain the projects on the resume. Why are you interested in this position when you do not have background in Video processing
Questions are based in ASIC flow and digital electronics .
how to overcome setup time and hold time violation
Design AND gate with 2:1 mux
How will you verify a memory mapped interface with one port?
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