Synchronous and Asynchronous FIFO
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
Setup, hold time. Which violation cannot be solved after chip tape out? Question on Automation side- using hash table.
Design a circuit with only one PMOS which functions as an inverter
Handed out a paper which has several questions on computer architecture. Basic questions such as pipeline structure and asked to draw binary sequence detector
Will you be able to easily commute to the location?
1) FIFO RTL design 2) how to optimize power 3) steps to take ECO
How will you verify for a DAC unit
3. If we use blocking inside always@(posedge clk) how will it be synthesized
Sequence detector for 111
"What is the purpose of the 'volatile' flag in the C programming language?"
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