1. Difference between SystemVerilog and Verilog. 2. Difference between nonblocking and blocking. 3. Difference between asynchronous and synchronous. 4. How can you observe and solve the problem if there is a timing violation (related to setup time and hold time)
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
what is clock uncertainty what is skew
What is the CMOS
I was asked to create XOR gate using only NOR gates.
State machine for detecting the sequence 101011
1. Began with Introduce Yourself. 2. Resume Question: You mention the Boot and Fuse Controller in your project. Tell me about that. 3. Further questions about the importance of Fuse in SoC. 4. Shift Preference? Open to relocation? 5. Do you have any questions you want to ask? Moving to technical: 1. Design an XNOR gate using a 2:1 Mux 2. Design a 1 Sticky Register
Synchronous and Asynchronous FIFO
Setup, hold time. Which violation cannot be solved after chip tape out? Question on Automation side- using hash table.
Design a circuit with only one PMOS which functions as an inverter
Handed out a paper which has several questions on computer architecture. Basic questions such as pipeline structure and asked to draw binary sequence detector
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