RTL program that covert j-k flip flop to D flip flop
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
Asked me about verilog and sv and TLM
Design a system that sorts 6 numbers from least to greatest using black boxes that can sort 2 numbers.
Asked about previous experience that would help me in the job here. was for an entry level position. also trying to find out if the training they provide would be useful to me to perform the tasks of the position
given two systems with an 8 bit connection. the sending system works at a frequency twice as fast as the system its sending to. what digital logic (gates, flip flops) should you put in order to have the systems work together? the slower system can have parallel computing
In technical interview, they asked: (1) about yourself (2) where did you hear the company (3) explain fundamentals regarding electronic elements e.g. diode, bjt, fet, opamp, capacitors (4) college thesis (5) what should they expect from you
What should be the size if it is receiving data and also loosing some packets ?
-Make a AND/OR gate out of muxes -Count the number of 1's in a 7 bit number using only full adders
1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.
Design OR gate using MUX
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