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Verification Engineer Interview Questions
2,556 verification engineer interview questions shared by candidates
C++ encapsulation, inheritance and polymorphism
Nothing was unexpected, very minimal behavioral questions. All the technical questions are regarding to computer architecture subjects.
Basic SV/UVM questions
Mainly about FSM's and basics of programming languages, It is a plus if you understand the perspective of a HDL.
Implement Linked list - Verification components in a testbench - Modify classic 5 stage pipeline to accommodate SMT -
What is your strength and weeknesses
testbench and test plan.
About digital electronics for VLSI domain
What is TLB cache? Why is it used?
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