Apr 8, 2021
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Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
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CMOS/VLSI, timing, logic on transistor level, Verilog question
Explain how setup time and hold time violations occur and what can be done to reduce there occurence? What is metastability?
Difference between latch and flip flop, Sequence detector design, Divide by n circuits for different values of n. Few scenarios of assertions, Verilog code for positive edge detector and negative edge detector, Setup and Hold time and few codes to debug and provide output. basic questions in digital on mux, questions on code synthesizing
UVM, SystemVerilog and PCIe protocol
write a program
Screening - shallow copy, deep copy (explain with code), polymorphism, virtual functions and overriding, sizing the dimensions of a multi dimensional array, constraints unique elements in a 2d array, sv events Panel - Constraints to generate unique address, aligned addresses, task for a driver with some conditions given (follow up -> response packet), using fork join for parallel driver, write driver for a dut which has 3 independent request channels and 2 independent response channels, sv code to find a number is multiple of 8, find output of sv snippet with mixed blocking and non blocking, use of $cast to check class type, declare and initialise a dynamic array, add an element to the same array while keeping previous ones as well, what are hazards in pipelined arch., dynamic branch prediction , data forwarding, randc without using rand, covergroup to cover overflow address, explain advantages of uvm over sv, how does a test start and end in uvm, what happens to the simulation if no objections are raised, how would you detect a hang in a test, write a task for time out
How to formally verify a cache.
Mostly asked basic digital design questions. Draw a sequential circuit, what is the makeup of an FPGA (LE, Registers etc), Draw a mod 10 counter, draw the schematic for a half adder. Once i drew the schematic for it i was then ask to draw it as if i had only NAND gates.
There were no out of the box questions.
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