Verification Engineer Interview Questions

2,564 verification engineer interview questions shared by candidates

UVM related questions.How to verify some components.How to verify a an old machine .X and Y dimensions of the screen in pixel was given.Was asked to write the test cases for the same.Was asked to a draw a fsm for a for traffic light signal .Questions related to clock skew,randomization and sorting algorithms
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Verification Engineer

Interviewed at Qualcomm

3.8
Sep 14, 2012

UVM related questions.How to verify some components.How to verify a an old machine .X and Y dimensions of the screen in pixel was given.Was asked to write the test cases for the same.Was asked to a draw a fsm for a for traffic light signal .Questions related to clock skew,randomization and sorting algorithms

Write a function in C that receives a string with brackets i.e: "({})[]" and returns true if the brackets are in correct form (like the example above) or false if the brackets aren't well placed like for example : "((]["
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Verification Design Engineer

Interviewed at Qualcomm

3.8
Mar 2, 2020

Write a function in C that receives a string with brackets i.e: "({})[]" and returns true if the brackets are in correct form (like the example above) or false if the brackets aren't well placed like for example : "((]["

Screening - shallow copy, deep copy (explain with code), polymorphism, virtual functions and overriding, sizing the dimensions of a multi dimensional array, constraints unique elements in a 2d array, sv events Panel - Constraints to generate unique address, aligned addresses, task for a driver with some conditions given (follow up -> response packet), using fork join for parallel driver, write driver for a dut which has 3 independent request channels and 2 independent response channels, sv code to find a number is multiple of 8, find output of sv snippet with mixed blocking and non blocking, use of $cast to check class type, declare and initialise a dynamic array, add an element to the same array while keeping previous ones as well, what are hazards in pipelined arch., dynamic branch prediction , data forwarding, randc without using rand, covergroup to cover overflow address, explain advantages of uvm over sv, how does a test start and end in uvm, what happens to the simulation if no objections are raised, how would you detect a hang in a test, write a task for time out
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GPU design verification engineer

Interviewed at Qualcomm

3.8
Mar 28, 2025

Screening - shallow copy, deep copy (explain with code), polymorphism, virtual functions and overriding, sizing the dimensions of a multi dimensional array, constraints unique elements in a 2d array, sv events Panel - Constraints to generate unique address, aligned addresses, task for a driver with some conditions given (follow up -> response packet), using fork join for parallel driver, write driver for a dut which has 3 independent request channels and 2 independent response channels, sv code to find a number is multiple of 8, find output of sv snippet with mixed blocking and non blocking, use of $cast to check class type, declare and initialise a dynamic array, add an element to the same array while keeping previous ones as well, what are hazards in pipelined arch., dynamic branch prediction , data forwarding, randc without using rand, covergroup to cover overflow address, explain advantages of uvm over sv, how does a test start and end in uvm, what happens to the simulation if no objections are raised, how would you detect a hang in a test, write a task for time out

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