Question asked: SV -> function can take fork_join?y/n ->to find the bit to represent 4069 = 2^(x) or log 2 base (32) ->Malloc() ->write a integer queue : rand int q[$]; -> task and functions UVM: Sequencer- Driver connection phasing name 3 base class related question
Given a block of memory with a 32 * 32 DFF cells and a Read/Write input DATA_write input Address input DATA_read output 1. describe all faults the system could have in the design process 2. write a verification code in any language of your choosing to check if the system functions as it shooed
There is RAM that has: A read/write control: “1 bit per read, 1 bit per write” means there is one control signal for read and one for write. These bits are asserted on the clock pulse, together with valid data and address. The interviewer then asks two things: “What issues in the system may fail the correct functionality?” This means: List all possible design / timing / logical / electrical problems that could cause the memory system not to work correctly. For example, wrong timing between clock and data, wrong use of read/write bits, address decoding errors, etc. (the exact list is up to the candidate). “Please develop an algorithm that will find all relevant issues, pre/post silicon.” This means: Propose a test method or verification algorithm that can detect these problems: Pre-silicon: using simulation, formal verification, or other design-time methods. Post-silicon: using real hardware tests, patterns, and read/write operations on the actual chip. Under Candidate coding, they give you two abstract operations that you can use in your algorithm: write(Address, RD/RW, Write_data) read(Address, RD/RW, Read_data) These are just function “primitives”: write(...) performs a write transaction to a specific address with some data and read/write configuration. read(...) performs a read transaction from a specific address and returns the data, using the RD/RW configuration.
write SVA according to given requirement
How many different LiDAR systems are you familiar with?
1. AND gate using MUX 2. FPGA And ASIC design flow 3. SRAM and DRAM 4. When do we use XOR gates 5. Buffers and invertors using XOR gates
Important to know pre-existing and future hardware products being developed, understanding about culture & fit
Round Robin arbitration issues in terms of how to verify
gone through the resume and asked about the experience over there. verifying FSM, DSP blocks etc were some questions
What's the different of rand and randc
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