swaping in sv, c and lot of arithmetic operations and bit of uvm.
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
General question about my past experience
All medium level questions in digital.
UVM, Scoreboard, regmodel, SV stuff
Standard introduction questions, background, education and experience What will you bring to the company that will benefit us the most.
Write a code for driver class in uvm.
digital electronics ,Verilog,SV and UVM
Write verilog code to generate a clock with 25% duty cycle , questions on case equality operator , basic gates using mux .
Verilog, Protocols , System Verilog , UVM
java script for selection sorting
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