Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
Design a Counter verification environment.
Sv constraints on memory block and region. GLS questions on debug flow.
What's your weak point?
Explain the latest project you undertook.
How would your friends describe you?
How does Level shifters work ? where they are placed
I just had been asked to define myself, and if have any questions.
How to verify a fifo?
I was asked to implement a 4-bit priority encoder using basic gates , and if i want to add one more bit how many gates i must add? and then to implement an SR flip-flop using D flip-flops — first with asynchronous Set, and then with asynchronous Reset.
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