DCG related, how to fix timing? Verilog RTL case x, case z, DFF, Dlatch Perl scripting TCL scripting in PT ICC Design patitioning
Physical Design Engineer Interview Questions
595 physical design engineer interview questions shared by candidates
Psychological and Analytic questions would take a conscious presence of mind to go through, The question includes technical knowledge with twists
Design a Flip Flop using transistors.
Q : explain all basic concepts of STA
basic on STA, Physical Design flow
Device characteristics, channel length modulation, body effect, why leakage increases as we continue to scale
VLSI lower power design techniques, FSM sequence detection, transistor layout, combinational circuit design, timing (setup, hold time), floorplanning, noise, crosstalk
Positive skew, Is half cycle path better for setup or hold?,UPF, power gating, PT scripts (get timing paths questions),ICC fixing, path groups, how to wake up the chip
How can you switch the value of two registers without additional space?
1st- Telephonic Round- Introduction, basics about PD flow, projects. 2nd- F2F round - A bit depth of CMOS, PD flow, real time problems of PD flow like calculate skew, slack. not selected after this round 3rd- F2F.
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