The interview covers static timing analysis and optimization, verilog coding, logic design puzzles like using MUX to achieve XOR gate.
Logic Design Engineer Interview Questions
66 logic design engineer interview questions shared by candidates
basic cache related questions
Questions were related to logic design and computer architecture. With a good understanding of pipeline design and out-of-order execution principles the questions were not too hard. The only question that I couldn't really solve was about the design of a scalable, fair arbiter. Expect questions about out-of-order execution algorithms, state machine design, and logic optimization.
Asked me to draw all Pipeline forwarding paths
Please tell me about your current job/project involved
Final year project, digital logics and soft skills
3) Different ways to close timing 3b) Timing closure with gates of different W/L ratio. 3c) Timing closure with gates of different no of inputs. Advantages and Disadvantages.
A lot of questions on clock domain crossing.
What are different kinds of muxes and latch and how they work?
design an arbiter - not priority based
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