How to make sure the 2-stage opamp is stable? How does the compensation work?
Analog Ic Design Engineer Interview Questions
68 analog ic design engineer interview questions shared by candidates
Psrr how do you reduce for a diff amp with active load pmos
We have lunch right now, you are welcome to join us
They asked me to draw a bandgap, PLL, sigma delta adc
It seems they open one of Razavi's electronics 1 lectures on youtube randomly, and copy one of his quizzes. Trick questions and hand-solving differential equations are also covered
If i wanted to work full time
general questions about RC circuits
Does the MOS have resistance when it has been turn on?
Questions included RC, LC questions, 2-stage OTA, Folded-Cascode OTAs, multiple current mirrors and biasing, Miller Compensation, Pole Splitting, Switched Cap circuits, LDOs, phase plots, Buck and boost converters and different types of compensations (current/voltage mode).
In an LDO what is harder to design, and nmos config or pmos config?
Viewing 1 - 10 interview questions