• Tell me about yourself • Rate yourself in Verilog, SV, UVM • Verilog code in generating clock pulse high in first 3 clock pulses and low in rest of clock pulses and again clock pulse should be high on 10th to 13th. This cycle should repeat. (10 min) • FSM 1011 overlap and explain that • Mealy and moore machine. • Project (communication protocol, fpga projects, ASIC project) • Setup and hold time • What is metastability • How to minimize the violation • Most priority violation setup or hold • General question • If you giving the opportunity in fpga or dsp you will ready to work • Tell me about NOKIA
