Write the verilog code for a divide-3 counter with 50% duty cycle.
Fpga Design Engineer Interview Questions
138 fpga design engineer interview questions shared by candidates
What is your experience with random constrained stimulus?
You have a device connected with a I2C bus. You send the data to the FIFO inside this device. How can you let the master know about FIFO overflow?
Easy questions like write DFF etc.
F: Was haben Sie in Ihrer letzten Position verdient?
Business manager: - can you introduce your profile - What's your experience on vhdl - could you describe your project - details about the project Human resources: - your profile - what has been the best and the worst experience in your job - your strength and weakness of your personality - what's your future plan in 3 and 7 years - What do you do in your free time
Solve these three tasks and send us back the solutions via an email.
Logic circuits and I2C interface
Tell me about yourself
How many ways to synchronize 2 asynchronized signal?
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